Internal design details of the Aura low-latency heterogeneous engine.

Aura SDK is structured to maximize throughput and minimize scheduling jitter on ARM64-NPU hardware boundaries.

Heterogeneous Scheduling Pipeline

Conventional execution paths rely on system service virtualization layers, introducing translation and context-switching overhead. Aura SDK interacts directly with the driver interfaces:

• Enclave Execution: Models are loaded into isolated hardware zones to protect memory contexts.
• Direct DSP Submissions: Tensor operations bypass CPU interruption points by writing directly to co-processor command rings.

                  +---------------------------------------+
                  |               Aura SDK                |
                  +---------------------------------------+
                                      |
                 Target Architecture Evaluation & Routing
                                      |
                 +--------------------+--------------------+
                 |                                         |
                 v                                         v
    [Native Genie Engine Engine]              [Aura Engine Backend (ORT)]
                 |                                         |
                 v                                         v
       Qualcomm AI Stack (QAIRT)                      ONNX Runtime
                 |                                         |
                 v                                         v
       Hexagon NPU Accelerator                    Oryon ARM64 CPU Cores
   (Compute Bound via HVX/HMX Tensor)         (Memory Bound via Cache Hierarchy)

Zero-Copy Shared Memory

A major bottleneck in hardware accelerators is the serialization and transfer of tensors over the PCIe or memory bus. Aura SDK solves this by allocating page-locked DDR memory accessible to both the CPU memory management unit and the Hexagon DSP MMU.

• Genie Engine Execution: Bypasses deep kernel validation layers by utilizing unsigned dynamic link libraries (.dll) to map ADSP memory spaces directly, reducing context-switch delays.
• Aura Engine Execution: Runs ONNX Runtime optimized for aarch64-pc-windows-msvc targeting the local Qualcomm Oryon CPU cores.