Understanding the optimization compilation pipeline from raw ONNX/PyTorch to compiled enclaves.

The Aura Compiler converts high-level tensor computation graphs (ONNX, PyTorch, or TensorFlow) into optimized binary enclaves containing target machine instructions for Qualcomm Snapdragon Hexagon tensor processors.

Compilation Pipeline

The translation occurs in three main stages:

1. Graph Optimization: Operator fusion (e.g., merging Conv2D and ReLU), dead code elimination, and memory layout conversion (NCHW to NHWC).
2. Quantization Alignment: Applying target scale profiles and hardware weight layout layouts.
3. Code Generation: Lowering target layers to Hexagon HVX/HMX vector assemblies and building the final binary artifact.

Compiling a Model

Use the compiler tool to compile an optimized ONNX model target:

aurac compile --input path/to/model.onnx --target hexagon-v73 --output-dir ./build --optimize-level 3

Optimization Strategies

To extract maximum performance from the Snapdragon co-processors:

• Tensor Layouts: Ensure static input dimensions where possible to prevent dynamic memory allocation overhead.
• Memory Tiling: Set partition sizing according to L2 cache specifications (typically 1.5MB to 8MB on Snapdragon platforms).
• Custom Kernels: Write custom tensor layers in C/C++ using the Aura SDK extension interface if built-in operator paths are not sufficient.