NPU Operator Matrix
Native hardware acceleration support status for standard ONNX/PyTorch operators on Snapdragon Hexagon co-processors.
This matrix defines standard neural network operator support across Aura Compiler target architectures. Operators not natively supported on Hexagon hardware are automatically delegated to CPU fallbacks via ONNX Runtime to maintain execution coverage.
Operator Compatibility Table
| ONNX Operator | Hexagon HVX Acceleration | Hexagon HMX (Tensor) Acceleration | Fallback Vector |
|---|---|---|---|
| Conv | Supported | Supported (Optimal) | N/A (Fully Hardware Accelerated) |
| Gemm / MatMul | Supported | Supported (Optimal) | N/A (Fully Hardware Accelerated) |
| Relu / PRelu | Supported | N/A | N/A (Fully Hardware Accelerated) |
| Softmax | Supported | N/A | N/A (Fully Hardware Accelerated) |
| Add / Mul / Sub | Supported | N/A | N/A (Fully Hardware Accelerated) |
| Reshape / Transpose | N/A | N/A | CPU Fallback (DMA memory transfer) |
| LayerNormalization | Supported | N/A | N/A (Fully Hardware Accelerated) |
| LSTM / GRU | Partial (v73+) | N/A | CPU Fallback (ONNX execution block) |
Resolving Fallbacks
When the compiler encounters an unsupported operator, it partitions the graph. The supported subgraphs are executed on the Hexagon NPU, and the remaining nodes are executed on the Snapdragon Oryon CPU. To avoid constant synchronization and memory copying overhead, minimize the occurrence of fallback operations inside deep model sections.